Camera Serial Interface
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The Camera Serial Interface (CSI) is a specification of the Mobile Industry Processor Interface (MIPI) Alliance. It defines an interface between a camera and a host processor.
The latest active interface specifications are: CSI-2 v4.2 (Dec 2025), CSI-3 v1.1 (March 2014), and CCS v1.1.1 (April 2023).
Standards
CSI-1
CSI-1 was the original standard MIPI interface for cameras. It emerged as an architecture to define the interface between a camera and a host processor. Its successors were MIPI CSI-2 and MIPI CSI-3, two standards that are still evolving.
CSI-2
The MIPI CSI-2 v1.0 specification was released in 2005. It uses either D-PHY or C-PHY (Both standards are set by the MIPI Alliance) as a physical layer option. The protocol is divided into the following layers: physical, lane merger, low-level protocol, pixel-to-byte conversion, and application.
In April 2017, the CSI-2 v2.0 specification was released. CSI-2 v2.0 brought support for RAW-16 and RAW-20 color depth, increase virtual channels from 4 to 32, Latency Reduction and Transport Efficiency (LRTE), Differential Pulse-Code Modulation (DPCM) compression and scrambling to reduce Power Spectral Density.
In September 2019, the CSI-2 v3.0 specification was released. CSI-2 v3.0 introduced Unified Serial Link (USL), Smart Region of Interest (SROI), End-of-Transmission Short Packet (EoTp) and support for RAW-24 color depth.
The most recent version, CSI-2 v4.2, was released in December 2025.
CSI-3
MIPI CSI-3 is a high-speed, bidirectional protocol primarily intended for image and video transmission between cameras and hosts within a multi-layered, peer-to-peer, UniPro-based M-PHY device network. It was originally released in 2012 and got re-released in version 1.1 in March 2014.
CCS
The Camera Command Set (CCS) v1.0 specification was released on November 30, 2017. CCS defines a standard set of functionalities for controlling image sensors using CSI-2.
The most recent version, CCS v1.1.1, was released in April 2023.
Technology and speeds
For electromagnetic interference reasons the system designer can select between two different clock rates (a and b) in each of the M-PHY speed levels.
| M-PHY speed | Clock rate | Bit rate |
|---|---|---|
| Gear 1 | G1a | 1.25 Gbit/s |
| G1b | 1.49 Gbit/s | |
| Gear 2 | G2a | 2.5 Gbit/s |
| G2b | 2.9 Gbit/s | |
| Gear 3 | G3a | 5 Gbit/s |
| G3b | 5.8 Gbit/s |