MCST-R1000

The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by MCST.

During development this microprocessor was designated as MCST-4R.

MCST R1000 Highlights

• implements the SPARC V9 instruction set architecture (ISA)
• quad-core
• core specifications: in-order, dual-issue superscalar 7-stage integer pipeline 9-stage floating-point pipeline VIS extensions 1 and 2 Multiply–accumulate unit 16 KB L1 instruction cache (parity protection) 32 KB L1 data cache (parity protection) size 7.6 mm2
• shared 2MB L2 cache (ECC protection)
• integrated memory controller
• integrated ccNUMA controller
• 1 GHz clock rate
• 90 nm process
• die size 128 mm2
• ~150 million transistors
• power consumption 15W