Sparcle

The Sparcle is an experimental 32-bit microprocessor chip developed in 1992 by a consortium of MIT, LSI Corporation, and Sun Microsystems. It was an evolution Sun's SPARC RISC architecture with features geared towards "large-scale multiprocessing". The chip was manufactured by LSI.

Besides these enhancements the Sparcle was otherwise unremarkable, incorporating 200,000 transistors and dissipating two watts. It included no cache and had a clock speed of less than 40MHz. The new features included:

• Features to tolerate and synchronize memory and communications latencies
• Features supporting fine-grained synchronization
• Features to initiate actions on remote processors and quickly respond to asynchronous events

The Sparcle was used to build the experimental Alewife computer at MIT.

External links

• Šilc, Jurij; etal. (1999). . Springer Science & Business Media. p.272. ISBN3-540-64798-8.
• Iannucci, Robert A.; etal. (1994). . Springer Science & Business Media. p.163. ISBN0-7923-9477-1.