ARM Cortex-A710
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The ARM Cortex-A710 is the successor to the ARM Cortex-A78, being the First-Generation Armv9 "big" Cortex CPU. It is the companion to the ARM Cortex-A510 "LITTLE" efficiency core. It was designed by ARM Ltd.'s Austin centre. It is the fourth and last iteration of Arm's Austin core family.
It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-X2, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.
Architecture changes in comparison with ARM Cortex-A78
The processor implements the following changes:
- Rename / Dispatch width: 5 (decreased from 6).
- 10-cycle pipeline (decreased from 11).
- One of only two ARMv9 cores to support EL0 AArch32, along with the ARM Cortex-A510.
Improvements:
- 30% more power efficient than Cortex-A78.
- 10% uplift in performance compared to Cortex-A78
- 2x ML uplift
Architecture comparison
"big" core
| μArch | Cortex-A77 | Cortex-A78 | Cortex-A710 | Cortex-A715 | Cortex-A720 | Cortex-A725 |
|---|---|---|---|---|---|---|
| Codename | Deimos | Hercules | Matterhorn | Makalu | Hunter | Chaberton |
| Peak clock speed | 2.6 GHz | ~3.0 GHz | - | |||
| Architecture | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |||
| AArch | - | 32-bit and 64-bit | 64-bit | |||
| Max In-flight | 160 | 160 | ? | 192+ | ? | - |
| L0 (Mops entries) | - | 1536 | 0 | - | ||
| L1 (I + D) (KiB) | 64 + 64 KiB | 32/64 + 32/64 KiB | 64 + 64 KiB | |||
| L2 Cache (KiB) | 256–512 KiB | 128–512 KiB | 0.25–1 MiB | |||
| L3 Cache (MiB) | 0–4 MiB | 0–8 MiB | 0–16 MiB | 0–32 MiB | ||
| Decode width | 4-way | 5-way | ||||
| Dispatch | 6 Mops/cycle | 5 Mops/cycle | ? | - |
Usage
- Qualcomm Snapdragon 7 Gen 1, Snapdragon 7+ Gen 2, Snapdragon 8/8+ Gen 1
- MediaTek Dimensity 9000/9000+
- Samsung Exynos 2200
See also
- ARM Cortex-X2, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family