ARM Cortex-A715
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The ARM Cortex-A715 is the second generation ARMv9 "big" Cortex CPU. Compared to its predecessor the Cortex-A710 the Cortex-A715 CPU is noted for having a 20% increase in power efficiency, and 5% improvement in performance. The Cortex-A715 shows comparable performance to the previous generation Cortex-X1 CPU.
This generation of chips starting with the A715 drops native 32-bit support. It forms part of Arm's Total Compute Solutions 2022 (TCS22) along with Arm's Cortex-X3, Cortex-A510, Arm Immortalis-G715 and CoreLink CI-700/NI-700.
Architecture changes in comparison with ARM Cortex-A710
The processor implements the following changes:
- Decode width: 5 (increased from 4)
- Removed micro-op (MOP) cache (previously 1.5k entries)
Usage
Architecture comparison
"big" core
| μArch | Cortex-A77 | Cortex-A78 | Cortex-A710 | Cortex-A715 | Cortex-A720 | Cortex-A725 |
|---|---|---|---|---|---|---|
| Codename | Deimos | Hercules | Matterhorn | Makalu | Hunter | Chaberton |
| Peak clock speed | 2.6 GHz | ~3.0 GHz | - | |||
| Architecture | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |||
| AArch | - | 32-bit and 64-bit | 64-bit | |||
| Max In-flight | 160 | 160 | ? | 192+ | ? | - |
| L0 (Mops entries) | - | 1536 | 0 | - | ||
| L1 (I + D) (KiB) | 64 + 64 KiB | 32/64 + 32/64 KiB | 64 + 64 KiB | |||
| L2 Cache (KiB) | 256–512 KiB | 128–512 KiB | 0.25–1 MiB | |||
| L3 Cache (MiB) | 0–4 MiB | 0–8 MiB | 0–16 MiB | 0–32 MiB | ||
| Decode width | 4-way | 5-way | ||||
| Dispatch | 6 Mops/cycle | 5 Mops/cycle | ? | - |
See also
- ARM Cortex-X3, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family