ARM Cortex-X3
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The ARM Cortex-X3 is the third generation X-series high-performance CPU core from Arm.
It forms part of Arm's Total Compute Solutions 2022 (TCS22) along with Arm's Cortex-A715, Cortex-A510, Immortalis-G715 and CoreLink CI-700/NI-700.
Architecture changes in comparison with ARM Cortex-X2
The processor implements the following changes:
- Decode width: 6 (increased from 5)
- Rename / Dispatch width: 8
- micro-op (MOP) cache: 1.5k entries (reduced from 3k)
- Reorder buffer (ROB): 320 entries (increased from 288)
- Execution ports: 15
- Pipeline length: 9 (reduced from 10)
Performance claims:
- 25% peak performance improvement over the ARM Cortex-X2 in smartphones
(3.3GHz, 1MB L2, 8MB L3).
- 11% IPC uplift over the ARM Cortex-X2, when based on the same process,
clock speed, and cache setup (also known as ISO-process).
Usage
Architecture comparison
"Prime" core
| uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 |
|---|---|---|---|---|---|---|
| Code name | Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk |
| Architecture | ARMv8.2 | ARMv9 | ARMv9.2 | |||
| Peak clock speed | ~3.0 GHz | ~3.3 GHz | ~3.4 GHz | ~3.8 GHz | ||
| Decode width | 4 | 5 | 6 | 10 | ||
| Dispatch | 6/cycle | 8/cycle | 10/cycle | |||
| Max in-flight | 2x 160 | 2x 224 | 2x 288 | 2x 320 | 2x 384 | 2x 768 |
| L0 (Mops entries) | 1536 | 3072 | 1536 | 0 | ||
| L1-I + L1-D | 32+32 KiB | 64+64 KiB | ||||
| L2 | 128–512 KiB | 0.25–1 MiB | 0.5–2 MiB | 2–3 MiB | ||
| L3 | 0–8 MiB | 0–16 MiB | 0–32 MiB |
See also
- ARM Cortex-A715, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family