List of ARM processors

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. Keil also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

Processors

Designed by ARM

Product family	ARM architecture	Processor	Feature	Cache (I/D), MMU	Typical MIPS @ MHz	Reference
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	0.33 DMIPS/MHz
ARM2aS	ARMv2a	ARM250	Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions	None, MEMC1a
ARM3	First integrated memory cache	4KB unified	0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit). ARMv3M first added long multiply instructions (32x32=64).	None	10MIPS @ 12MHz
ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)	4KB unified	28MIPS @ 33MHz
ARM610	As ARM60, cache, no coprocessor bus	4KB unified	17MIPS @ 20MHz 0.65 DMIPS/MHz
ARM7	ARMv3	ARM700	coprocessor bus (for FPA11 floating-point unit)	8KB unified	40MHz
ARM710	As ARM700, no coprocessor bus	8KB unified	40MHz
ARM710a	As ARM710, also used as core of ARM7100	8KB unified	40MHz 0.68 DMIPS/MHz
ARM7T	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing	None	15MIPS @ 16.8MHz 63 DMIPS @ 70MHz
ARM710T	As ARM7TDMI, cache	8KB unified, MMU	36MIPS @ 40MHz
ARM720T	As ARM7TDMI, cache	8KB unified, MMU with FCSE (FastContext Switch Extension)	60MIPS @ 59.8MHz
ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions	None
ARM8	ARMv4	ARM810	5-stage pipeline, static branch prediction, double-bandwidth memory	8KB unified, MMU	84MIPS @ 72MHz 1.16 DMIPS/MHz
ARM9T	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	None
ARM920T	As ARM9TDMI, cache	16KB / 16KB, MMU with FCSE (Fast Context Switch Extension)	200MIPS @ 180MHz
ARM922T	As ARM9TDMI, caches	8KB / 8KB, MMU
ARM940T	As ARM9TDMI, caches	4KB / 4KB, MPU
ARM9E	ARMv5TE	ARM946E-S	Thumb, enhanced DSP instructions, caches	Variable, tightly coupled memories, MPU
ARM966E-S	Thumb, enhanced DSP instructions	No cache, TCMs
ARM968E-S	As ARM966E-S	No cache, TCMs
ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions	Variable, TCMs, MMU	220MIPS @ 200MHz
ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	No caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)	32KB / 32KB, MMU
ARM1022E	As ARM1020E	16KB / 16KB, MMU
ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)	Variable, MMU or MPU
ARM11	ARMv6	ARM1136J(F)-S	8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access	Variable, MMU	740 @ 532–665MHz (i.MX31 SoC), 400–528MHz
ARMv6T2	ARM1156T2(F)-S	9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions	Variable, MPU
ARMv6Z	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	Variable, MMU + TrustZone	965DMIPS @ 772MHz
ARMv6K	ARM11MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	Variable, MMU
SecurCore	ARMv6-M	SC000	As Cortex-M0		0.9 DMIPS/MHz
ARMv4T	SC100	As ARM7TDMI
ARMv7-M	SC300	As Cortex-M3		1.25 DMIPS/MHz
Cortex-M	ARMv6-M	Cortex-M0	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, no MPU	0.84 DMIPS/MHz
Cortex-M0+	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	0.93 DMIPS/MHz
Cortex-M1	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory	Optional cache, 0–1024KB I-TCM, 0–1024KB D-TCM, no MPU	136 DMIPS @ 170MHz, (0.8DMIPS/MHz FPGA-dependent)
ARMv7-M	Cortex-M3	Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz
ARMv7E-M	Cortex-M4	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz (1.27 w/FPU)
Cortex-M7	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions	0−64KB I-cache, 0−64KB D-cache, 0–16MB I-TCM, 0–16MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions	2.14 DMIPS/MHz
ARMv8-M Baseline	Cortex-M23	Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone	Optional cache, no TCM, optional MPU with 16 regions	1.03 DMIPS/MHz
ARMv8-M Mainline	Cortex-M33	Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor	Optional cache, no TCM, optional MPU with 16 regions	1.50 DMIPS/MHz
Cortex-M35P	Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor	Built-in cache (with option 2–16KB), I-cache, no TCM, optional MPU with 16 regions	1.50 DMIPS/MHz
ARMv8.1-M Mainline	Cortex-M52			1.60 DMIPS/MHz
Cortex-M55			1.69 DMIPS/MHz
Cortex-M85			3.13 DMIPS/MHz
Cortex-R	ARMv7-R	Cortex-R4	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic	0–64KB / 0–64KB, 0–2 of 0–8MB TCM, opt. MPU with 8/12 regions	1.67 DMIPS/MHz
Cortex-R5	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)	0–64KB / 0–64KB, 0–2 of 0–8MB TCM, opt. MPU with 12/16 regions	1.67 DMIPS/MHz
Cortex-R7	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP	0–64KB / 0–64KB,? of 0–128KB TCM, opt. MPU with 16 regions	2.50 DMIPS/MHz
Cortex-R8	TBD	0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions	2.50 DMIPS/MHz
ARMv8-R	Cortex-R52	TBD	0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions	2.09 DMIPS/MHz
Cortex-R52+	TBD	0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions	2.09 DMIPS/MHz
Cortex-R82	TBD	16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM, opt MPU with 32+32 regions	3.41 DMIPS/MHz
Cortex-A (32-bit)	ARMv7-A	Cortex-A5	Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	4−64KB / 4−64KB L1, MMU + TrustZone	1.57DMIPS/MHz per core
Cortex-A7	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design	8−64KB / 8−64KB L1, 0–1MB L2, MMU + TrustZone	1.9 DMIPS/MHz per core
Cortex-A8	Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline	16–32KB / 16–32KB L1, 0–1MB L2 opt. ECC, MMU + TrustZone	2.0DMIPS/MHz
Cortex-A9	Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	16–64KB / 16–64KB L1, 0–8MB L2 opt. parity, MMU + TrustZone	2.5 DMIPS/MHz per core, 10,000DMIPS @ 2GHz on Performance Optimized TSMC 40G (dual-core)
Cortex-A12	Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	32−64 KB	3.0 DMIPS/MHz per core
Cortex-A15	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline	32KB w/parity / 32KB w/ECC L1, 0–4MB L2, L2 has ECC, MMU + TrustZone	At least 3.5DMIPS/MHz per core (up to 4.01DMIPS/MHz depending on implementation)
Cortex-A17	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP	32 KB L1, 256KB–8MB L2 w/optional ECC	2.8DMIPS/MHz
ARMv8-A	Cortex-A32	Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline	8–64KB w/optional parity / 8−64KB w/optional ECC L1 per core, 128KB–1MB L2 w/optional ECC shared
Cortex-A (64-bit)	ARMv8-A	Cortex-A34	Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64KB w/parity / 8−64KB w/ECC L1 per core, 128KB–1MB L2shared, 40-bit physical addresses
Cortex-A35	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64KB w/parity / 8−64KB w/ECC L1 per core, 128KB–1MB L2shared, 40-bit physical addresses	1.78 DMIPS/MHz
Cortex-A53	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64KB w/parity / 8−64KB w/ECC L1 per core, 128KB–2MB L2shared, 40-bit physical addresses	2.3 DMIPS/MHz
Cortex-A57	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline	48 KB w/DED parity / 32KB w/ECC L1 per core; 512KB–2MB L2shared w/ECC; 44-bit physical addresses	4.1–4.8DMIPS/MHz
Cortex-A72	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline	48 KB w/DED parity / 32KB w/ECC L1 per core; 512KB–2MB L2shared w/ECC; 44-bit physical addresses	6.3-7.3 DMIPS/MHz
Cortex-A73	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline	64 KB / 32−64KB L1 per core, 256KB–8MB L2shared w/ optional ECC, 44-bit physical addresses	7.4-8.5 DMIPS/MHz
ARMv8.2-A	Cortex-A55	Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	16−64 KB / 16−64KB L1, 256KB L2 per core, 4MB L3 shared	3 DMIPS/MHz
Cortex-A65	Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT
Cortex-A65AE	As ARM Cortex-A65, adds dual core lockstep for safety applications	64 / 64 KB L1, 256KB L2 per core, 4MB L3 shared
Cortex-A75	Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline	64 / 64 KB L1, 512KB L2 per core, 4MB L3 shared	8.2-9.5 DMIPS/MHz
Cortex-A76	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline	64 / 64 KB L1, 256−512KB L2 per core, 512KB−4MB L3 shared	10.7-12.4 DMIPS/MHz
Cortex-A76AE	As ARM Cortex-A76, adds dual core lockstep for safety applications
Cortex-A77	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline	1.5K L0 MOPs cache, 64 / 64KB L1, 256−512KB L2 per core, 512KB−4MB L3 shared	13-16 DMIPS/MHz
Cortex-A78
Cortex-A78AE	As ARM Cortex-A78, adds dual core lockstep for safety applications
Cortex-A78C
ARMv9-A	Cortex-A510
Cortex-A710
Cortex-A715
ARMv9.2-A	Cortex-A320
Cortex-A520
Cortex-A720
Cortex-A725
Cortex-X	ARMv8.2-A	Cortex-X1	Performance-tuned variant of Cortex-A78
ARMv9-A	Cortex-X2		64 / 64 KB L1, 512–1024 KiB L2 per core, 512 KiB–8 MiB L3 shared
Cortex-X3		64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–16 MiB L3 shared
ARMv9.2-A	Cortex-X4		64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–32 MiB L3 shared
Cortex-X925		64 / 64 KB L1, 2048–3072 KiB L2 per core, 512 KiB–32 MiB L3 shared
Neoverse	ARMv8.2-A	Neoverse N1	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline	64 / 64 KB L1, 512−1024KB L2 per core, 2−128MB L3 shared, 128MB system level cache
Neoverse E1	Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT	32−64 KB / 32−64KB L1, 256KB L2 per core, 4MB L3 shared
ARMv8.4-A	Neoverse V1
ARMv9-A	Neoverse N2
Neoverse V2
ARMv9.2-A	Neoverse N3
Neoverse V3
C1	ARMv9.3-A	C1-Ultra	Successor to Cortex X925 Native SME2 instruction set support introduced	64 / 128 KB L1, 2048–3072 KiB L2 per core, 256 KiB–32 MiB L3 shared, 40-bit MMU, SVE2 + SME2
C1-Premium	New tier	64 / 128 KB L1, 512–1024 KiB L2 per core, 256 KiB–32 MiB L3 shared, 40-bit MMU, SVE2 + SME2
C1-Pro	Successor to Cortex A725 Native SME2 instruction set support introduced	64 / 64 KB L1, 128–1024 KiB L2 per core, 256 KiB–32 MiB L3 shared, 40-bit MMU, SVE2 + SME2
C1-Nano	Successor to Cortex A520 Native SME2 instruction set support introduced	32/64 / 64 KB L1, 128–512 KiB L2 per core, 256 KiB–32 MiB L3 shared, 40-bit MMU, SVE2 + SME2
ARM family	ARM architecture	ARM core	Feature	Cache (I/D), MMU	Typical MIPS @ MHz	Reference

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Product family	ARM architecture	Processor	Feature	Cache (I/D), MMU	Typical MIPS @ MHz
StrongARM (Digital)	ARMv4	SA-110	5-stage pipeline	16KB / 16KB, MMU	100–233MHz 1.0 DMIPS/MHz
SA-1100	derivative of the SA-110	16KB / 8KB, MMU
Faraday (Faraday Technology)	ARMv4	FA510	6-stage pipeline	Up to 32KB / 32KB cache, MPU	1.26 DMIPS/MHz 100–200MHz
FA526	Up to 32KB / 32KB cache, MMU	1.26MIPS/MHz 166–300MHz
FA626	8-stage pipeline	32KB / 32KB cache, MMU	1.35 DMIPS/MHz 500MHz
ARMv5TE	FA606TE	5-stage pipeline	No cache, no MMU	1.22 DMIPS/MHz 200MHz
FA626TE	8-stage pipeline	32KB / 32KB cache, MMU	1.43MIPS/MHz 800MHz
FMP626TE	8-stage pipeline, SMP	1.43MIPS/MHz 500MHz
FA726TE	13 stage pipeline, dual issue	2.4 DMIPS/MHz 1000MHz
XScale (Intel / Marvell)	ARMv5TE	XScale	7-stage pipeline, Thumb, enhanced DSP instructions	32KB / 32KB, MMU	133–400MHz
Bulverde	Wireless MMX, wireless SpeedStep added	32KB / 32KB, MMU	312–624MHz
Monahans	Wireless MMX2 added	32KB / 32KB L1, optional L2cache up to 512KB, MMU	Up to 1.25GHz
Sheeva (Marvell)	ARMv5	Feroceon	5–8 stage pipeline, single-issue	16KB / 16KB, MMU	600–2000MHz
Jolteon	5–8 stage pipeline, dual-issue	32KB / 32KB, MMU
PJ1 (Mohawk)	5–8 stage pipeline, single-issue, Wireless MMX2	32KB / 32KB, MMU	1.46 DMIPS/MHz 1.06GHz
ARMv6 / ARMv7-A	PJ4	6–9 stage pipeline, dual-issue, Wireless MMX2, SMP	32KB / 32KB, MMU	2.41DMIPS/MHz 1.6GHz
Snapdragon (Qualcomm)	ARMv7-A	Scorpion	1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)	256KB L2 per core	2.1 DMIPS/MHz per core
Krait	1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)	4KB / 4KB L0, 16KB / 16KB L1, 512KB L2 per core	3.3 DMIPS/MHz per core
ARMv8-A	Kryo	4 cores.	?	Up to 2.2GHz (6.3 DMIPS/MHz)
A series (Apple)	ARMv7-A	Swift	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON	L1: 32KB / 32KB, L2: 1MB shared	3.5 DMIPS/MHz per core
ARMv8-A	Cyclone	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar.	L1: 64KB / 64KB, L2: 1MB shared SLC: 4MB	1.3 or 1.4GHz
ARMv8-A	Typhoon	2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64	L1: 64KB / 64KB, L2: 1MB or 2MB shared SLC: 4MB	1.4 or 1.5GHz
ARMv8-A	Twister	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64	L1: 64KB / 64KB, L2: 2MB shared SLC: 4MB or 0MB	1.85 or 2.26GHz
ARMv8-A	Hurricane and Zephyr	Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar.	L1: 64KB / 64KB, L2: 3MB or 8MB shared L1: 32KB / 32KB. L2: none SLC: 4MB or 0MB	2.34 or 2.38GHz 1.05GHz
ARMv8.2-A	Monsoon and Mistral	Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode,?-issue, 11-wide Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift.	L1I: 128KB, L1D: 64KB, L2: 8MB shared L1: 32KB / 32KB, L2: 1MB shared SLC: 4MB	2.39GHz 1.70GHz
ARMv8.3-A	Vortex and Tempest	Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode,?-issue, 11-wide Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift.	L1: 128KB / 128KB, L2: 8MB shared L1: 32KB / 32KB, L2: 2MB shared SLC: 8MB	2.49GHz 1.59GHz
ARMv8.4-A	Lightning and Thunder	Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode,?-issue, 11-wide Thunder: 4 cores. AArch64, out-of-order, superscalar.	L1: 128KB / 128KB, L2: 8MB shared L1: 32KB / 48KB, L2: 4MB shared SLC: 16MB	2.66GHz 1.73GHz
ARMv8.5-A	Firestorm and Icestorm	Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode,?-issue, 14-wide Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode,?-issue, 7-wide.	L1: 192KB / 128KB, L2: 8MB shared L1: 128KB / 64KB, L2: 4MB shared SLC: 16MB	3.0GHz 1.82GHz
ARMv8.6-A	Avalanche and Blizzard	Avalanche: 2 cores. AArch64, out-of-order, superscalar, 8-decode,?-issue, 14-wide Blizzard: 4 cores. AArch64, out-of-order, superscalar, 4-decode,?-issue, 8-wide.	L1: 192KB / 128KB, L2: 12MB shared L1: 128KB / 64KB, L2: 4MB shared SLC: 32MB	2.93 or 3.23GHz 2.02GHz
ARMv8.6-A	Everest and Sawtooth	Everest: 2 cores. AArch64, out-of-order, superscalar, 8-decode,?-issue, 14-wide Sawtooth: 4 cores. AArch64, out-of-order, superscalar, 4-decode,?-issue, 8-wide.	L1: 192KB / 128KB, L2: 16MB shared L1: 128KB / 64KB, L2: 4MB shared SLC: 24MB	3.46GHz 2.02GHz
ARMv8.6-A	Apple A17 Pro	Apple A17 Pro (P-cores): 2 cores. AArch64, out-of-order, superscalar, 8-decode,?-issue, 14-wide Apple A17 Pro (E-cores): 4 cores. AArch64, out-of-order, superscalar, 4-decode,?-issue, 8-wide.	L1: 192KB / 128KB, L2: 16MB shared L1: 128KB / 64KB, L2: 4MB shared SLC: 24MB	3.78GHz 2.11GHz
M series (Apple)	ARMv8.5-A	Firestorm and Icestorm	Firestorm: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, 8-issue, 14-wide Icestorm: 2 or 4 cores. AArch64, out-of-order, superscalar, 4-decode, 4-issue, 7-wide.	L1: 192KB / 128KB, L2: 12, 24 or 48MB shared L1: 128KB / 64KB, L2: 4 or 8MB shared SLC: 8, 24, 48 or 96MB	3.2-3.23GHz 2.06GHz
ARMv8.6-A	Avalanche and Blizzard	Avalanche: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, 8-issue, 14-wide Blizzard: 4 or 8 cores. AArch64, out-of-order, superscalar, 4-decode, 4-issue, 8-wide.	L1: 192KB / 128KB, L2: 16, 32 or 64MB shared L1: 128KB / 64KB, L2: 4 or 8MB shared SLC: 8, 24, 48 or 96MB	3.49GHz 2.42GHz
ARMv8.6-A	Apple M3	Apple M3 (P-cores): 4, 5, 6, 10, 12 or 16 cores. AArch64, out-of-order, superscalar, 9-decode, 9-issue, 14-wide Apple M3 (E-cores): 4 or 6 cores. AArch64, out-of-order, superscalar, 5-decode, 5-issue, 8-wide.	L1: 192KB / 128KB, L2: 16, 32 or 64MB shared L1: 128KB / 64KB, L2: 4 or 8MB shared SLC: 8, 24, 48 or 96MB	4.05GHz 2.75GHz
ARMv9.2-A	Apple M4	Apple M4 (P-cores): 3 or 4 cores. AArch64, out-of-order, superscalar, 10-decode, 10-issue, 16-wide Apple M4 (E-cores): 6 cores. AArch64, out-of-order, superscalar, 5-decode, 5-issue, 8-wide.	L1: 192KB / 128KB, L2: 16, 32 or 64MB shared L1: 128KB / 64KB, L2: 4 or 8MB shared SLC: 8, 24, 48 or 96MB	4.40GHz 2.85GHz
X-Gene (Applied Micro)	ARMv8-A	X-Gene	64-bit, quad issue, SMP, 64 cores	Cache, MMU, virtualization	3GHz (4.2 DMIPS/MHz per core)
Denver (Nvidia)	ARMv8-A	Denver	2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128MB optimization cache, Denver1: 28nm, Denver2:16nm	128KB I-cache/64KB D-cache	Up to 2.5GHz
Carmel (Nvidia)	ARMv8.2-A	Carmel	2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization,?MB optimization cache, functional safety, dual execution, parity & ECC	?KB I-cache/?KB D-cache	Up to?GHz
ThunderX (Cavium)	ARMv8-A	ThunderX	64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips)	?	Up to 2.2GHz
K12 (AMD)	ARMv8-A	K12	?	?	?
Exynos (Samsung)	ARMv8-A	M1 ("Mongoose")	4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order	64KB I-cache/32KB D-cache, L2: 16-way shared 2MB	5.1 DMIPS/MHz (2.6GHz)
ARMv8-A	M2 ("Mongoose")	4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order	64KB I-cache/32KB D-cache, L2: 16-way shared 2MB	2.3GHz
ARMv8-A	M3 ("Meerkat")	4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64KB I-cache/64KB D-cache, L2: 8-way private 512KB, L3: 16-way shared 4MB	2.7GHz
ARMv8.2-A	M4 ("Cheetah")	2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64KB I-cache/64KB D-cache, L2: 8-way private 1MB, L3: 16-way shared 3MB	2.73GHz
ARMv8.2-A	M5 ("Lion")	2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64KB I-cache/64KB D-cache, L2: 8-way shared 2MB, L3: 12-way shared 3MB	2.73GHz

Timeline

The following table lists each core by the year it was announced.

ARM Classic

Year	Classic cores
ARM1-3	ARM6	ARM7	ARM8	ARM9	ARM10	ARM11
1985	ARM1
1986	ARM2
1989	ARM3
1992	ARM250
1993		ARM60 ARM610	ARM700
1994			ARM710 ARM7DI ARM7TDMI
1995			ARM710a
1996				ARM810
1997			ARM710T ARM720T ARM740T
1998					ARM9TDMI ARM940T
1999					ARM9E-S ARM966E-S
2000					ARM920T ARM922T ARM946E-S	ARM1020T
2001			ARM7EJ-S ARM7TDMI-S		ARM9EJ-S ARM926EJ-S	ARM1020E ARM1022E
2002						ARM1026EJ-S	ARM1136J(F)-S
2003					ARM968E-S		ARM1156T2(F)-S ARM1176JZ(F)-S
2004
2005							ARM11MPCore
2006					ARM996HS

ARM Cortex / Neoverse

Year	Cortex cores	Neoverse cores
Microcontroller (Cortex-M)	Real-time (Cortex-R)	Application (Cortex-A) (32-bit)	Application (Cortex-A) (64-bit)	Application (Cortex-X) (64-bit)	Application (Neoverse) (64-bit)
2004	Cortex-M3
2005			Cortex-A8
2006
2007	Cortex-M1		Cortex-A9
2008
2009	Cortex-M0		Cortex-A5
2010	Cortex-M4(F)		Cortex-A15
2011		Cortex-R4(F) Cortex-R5(F) Cortex-R7(F)	Cortex-A7
2012	Cortex-M0+			Cortex-A53 Cortex-A57
2013			Cortex-A12
2014	Cortex-M7(F)		Cortex-A17
2015				Cortex-A35 Cortex-A72
2016	Cortex-M23 Cortex-M33(F)	Cortex-R8(F) Cortex-R52(F)	Cortex-A32	Cortex-A73
2017				Cortex-A55 Cortex-A75
2018	Cortex-M35P(F)			Cortex-A65 Cortex-A65AE Cortex-A76 Cortex-A76AE
2019			Cortex-A34	Cortex-A77		Neoverse E1 Neoverse N1
2020	Cortex-M55(F)	Cortex-R82(F)		Cortex-A78 Cortex-A78AE Cortex-A78C	Cortex-X1	Neoverse V1
2021				Cortex-A510 Cortex-A710	Cortex-X2	Neoverse E2 Neoverse N2
2022	Cortex-M85(F)	Cortex-R52+(F)		Cortex-A715	Cortex-X3	Neoverse V2
2023	Cortex-M52(F)			Cortex-A520 Cortex-A720	Cortex-X4	Neoverse E3 Neoverse N3
2024		Cortex-R82AE		Cortex-A520AE Cortex-A720AE Cortex-A725	Cortex-X925	Neoverse V3 Neoverse V3AE Neoverse VN
2025				Cortex-A320 Cortex-A530 Cortex-A730	Cortex-X930	Neoverse E4 Neoverse N4 Neoverse V4